Engineers have found a way to command the speed of light within a silicon-based chip, adjusting delays, synchronisation and buffering exactly when needed. The advance, detailed in a peer-reviewed paper, rests on meticulous modelling rather than grand promises, demonstrating how careful design can extract fresh capability from established optical physics.
Researchers at Seoul National University and the University of Seoul developed a programmable photonic integrated circuit that can slow light on demand. Published online on 28 June 2026 in the journal Advanced Science, the work reinterprets the familiar phenomenon of coupled-resonator-induced transparency through a spinor representation and dual-channel gauge fields. This framework treats what were once fixed bright and dark modes as a single controllable degree of freedom.
The chip therefore permits dynamic adjustment of optical pulse speed, signal delay times, bandwidth, shape and frequency conversion. These parameters can be tuned without compromising processing performance. Such flexibility supplies the delays, synchronisation and buffering capabilities that photonic circuits have long required yet struggled to deliver in a single device.
Rigorous testing under realistic constraints
Numerical simulations on a silicon nitride platform confirmed reliable operation even when confronted with the imperfections of actual manufacture and deployment. Material losses, variations in resonator quality, backscattering, coupling fluctuations, phase errors and thermal crosstalk were all included. The models held steady, suggesting the design tolerates the conditions it would meet on a real wafer.
This grounded validation matters. Previous approaches to slow-light effects tended to lock devices into preset characteristics, limiting their usefulness. By adding controllable loop couplers and unifying the underlying modes, the new circuit consolidates multiple optical signal-processing tasks into one component. The result points toward reduced energy consumption, lower cost and simpler architectures in areas from data-centre interconnects to optical computing.
The paper itself remains at the stage of analytical models, numerical simulations and three-dimensional electromagnetic validations. Plans for experimental realisation and scaling to larger silicon-photonics platforms lie ahead. That sequence, from theory to hardware, reflects the patient engineering tradition that has steadily expanded the reach of photonic technologies.
